The one-transistor memory cell used in most dynamic semiconductor random access memories relies on charge storage on a capacitive element, with the charge gated into the capacitor through the one transistor of the cell. To maximize the density of memory cells on each semiconductor chip, it is desirable to minimize the size of each cell. The cell size is largely determined by the area necessary to store a given amount of charge (the amount being determined by the sensitivity of the associated charge-sensing circuitry) which is inversely proportional to the capacitance per unit area of the cell. Maximization of the per unit area capacitance is therefore desired.
The typical one-transistor memory cell uses an MOS capacitor whose capacitance is composed of the parallel combination of two capacitances: (1) the capacitance between the field plate and the inversion layer (the "oxide capacitance"), and (2) the depletion-layer capacitance between the inversion layer and the substrate. At typical operating voltages, the oxide capacitance is generally much greater than the depletion-layer capacitance, especially when lightly doped substrates are used to reduce capacitance and transistor body effect in other parts of the circuit. The resulting cell size necessary to insure adequate charge storage in prior art devices has been relatively large.